The present invention relates to an integrated circuit and, more particularly, to integrated circuits having self test capabilities for monitoring connections from their external voltage-and-current supplies to their internal more positive and more negative conductors.
As integrated circuits have become larger and more complex, a number of connection problems have arisen. One of the more difficult problems is related to the supply of voltage and current between the printed wiring board and the integrated circuit which is mounted thereon. Modern integrated circuits, such as ASIC and VLSI devices, have become so large that a single pin connection cannot carry the maximum operating current of the circuit without causing unacceptable local voltage changes. Modern integrated circuits typically resolve this problem by providing a more positive conductor grid and a more negative conductor grid within the integrated circuit. These grids, then, are connected to multiple pins which are connected to the more positive or more negative conductors of the voltage-and-current supply.
The physical structure where each pin physically and electrically joins to its respective conductor grid is known as a pad. This means that the voltage and current are connected from the voltage-and-current conductors of the printed wiring board, through a number of pins to their internal pads on the integrated circuit substrate. From the pads, the voltage and current is connected to the more positive conductor grid or the more negative conductor grid.
Since multiple pins are connected from an electrically common external point, i.e. either the more positive or the more negative conductor of the voltage and current supply, to a electrically common internal point, i.e. either the more positive or the more negative conductor grids, the pins to the more positive conductor grid are all electrically in parallel when the integrated circuit is mounted on its printed wiring board. Similarly, the pins to the more negative conductor grid are all electrically in parallel with each other. As long as each pin has the same voltage and current characteristics as its paralleled pins between its respective conductor grid and its printed wiring board conductors, the current will divide evenly among the paralleled pins according to the well known current dividing principle. Ideally then, when the integrated circuit is required by its input and output conditions to draw maximum current from the voltage-and-current supply, the maximum current will be drawn evenly by the pins and local voltage changes in the form of noise will not occur within the integrated circuit.
One major disadvantage of having multiple paralleled pins carry the supply current is that it is virtually impossible to detect a problem of a faulty connection between one of the printed wiring board supply conductors and the corresponding integrated circuit conductor grid. For example, because the multiple pins are connected in parallel from the more positive conductor of the supply on the outside of the integrated circuit package to the more positive grid of the integrated circuit on the inside, or from the less positive conductor of the supply voltage on the outside of the integrated circuit package to the less positive grid of the integrated circuit on the inside, it is impossible to test and verify that all of the paralleled pins have good connections after the package has been sealed and mounted. Thus, it is difficult or impossible to adequately test the condition of paralleled supply pins on integrated circuits, once the integrated circuit has been mounted to its printed wiring board. Therefore, a faulty connection of one of the paralleled supply pins will probably go unnoticed until the integrated circuit is called upon by its input or output conditions to drawing maximum current. However, when such a maximum current condition occurs, voltage pulses induced by a faulty connection may cause random data errors to be outputted from the integrated circuit instead of the proper data.